1. Field of the Invention
The present invention relates to a waveform generation apparatus including a pattern generator, a setup cycle correction method that corrects a setup cycle of the pattern generator, and a semiconductor test apparatus including the waveform generation apparatus. More particularly, it relates to a waveform generation apparatus which moves spurious noise produced in the vicinity of a carrier in an output signal from a timing generator included in the waveform generation apparatus so as to be distant from the carrier in terms of frequency, with the result that the spurious noise can be removed by a PLL (phase locked loop) provided in the waveform generation apparatus, a setup cycle correction method, and a semiconductor test apparatus.
2. Description of the Related Art
In general, a semiconductor test apparatus supplies a test pattern of a frequency in accordance with an operating frequency of an electronic device to the electronic device to perform a test. Furthermore, when the electronic device as a test target has a plurality of cores having different operating frequencies, the respective cores are sequentially tested.
Meanwhile, in order to perform the test of the electronic device in detail, it is necessary to perform the test while the plurality of cores are simultaneously operated. Therefore, the conventional semiconductor test apparatus generates a plurality of clocks in accordance with respective operating frequencies of the plurality of cores and simultaneously operates the cores based on the plurality of generated clocks to perform the test.
In recent years, a test of supplying the plurality of clocks to the respective cores in the electronic device in synchronization with each other (a multitime domain) is conducted. This is a test which is performed for a device having a plurality of different interface speeds.
FIG. 9 shows a structure of this type of multitime domain test apparatus (a waveform generation apparatus).
It is to be noted that the waveform generation apparatus depicted in FIG. 9 is mounted in a semiconductor test apparatus in order to perform the multitime domain test.
As shown in the drawing, a waveform generation apparatus (a semiconductor test apparatus) 100 includes a pattern generator 110, a timing generator 120, and a PLL 130.
Here, the pattern generator 110 generates a cycle pattern based on a setup cycle.
The timing generator 120 outputs the cycle pattern input from the pattern generator 110 as a high-precision variable clock based on a reference clock.
It is to be noted that various improvements have been proposed for the pattern generator or the timing generator, for example, as disclosed by Japanese Patent Application No. 79545-1992.
The PLL (Phase Locked Loop) 130 removes spurious noise from the high-precision variable clock output from the timing generator 120.
Here, the spurious noise means an unnecessary component produced in a signal (in this specification, the high-precision variable clock).
A cause of the occurrence of this spurious noise will now be explained with reference to FIGS. 10 to 13.
As shown in FIG. 10, the timing generator 120 has delay circuits 121-1 to 121-n in units of the reference clock, and a high-precision variable delay circuit 122. Here, the timing generator 120 integrates a phase with respect to the reference clock every time it receives a cycle pattern signal, and switches the delay circuits 121-1 to 121-n to corresponding one in real time.
Furthermore, as shown in FIG. 11, when a difference from the setup cycle with respect to an integral multiple of a reference clock cycle is sufficiently small, a delay path varies every time the integrated phase reaches a resolution α concerning the setup cycle of the timing generator, and a phase error also fluctuates. Moreover, when the integrated phase reaches the reference clock cycle, an amount corresponding to a cycle is subtracted, thereby realizing a delay of one cycle. When a phase fluctuation in accordance with the setup cycle periodically occurs, the spurious noise is produced.
It is to be noted that a position of the produced spurious noise with respect to a carrier can be obtained from fluctuation cycles T1 and T2 of the phase error depicted in FIG. 11.
Now, the fluctuation cycle T1 will be explained with reference to FIG. 12.
As shown in the drawing, for example, when a reference clock cycle is 4 ns and a RATE cycle set value is 9 ns (=4×2+20 ns), a cycle pattern having a cycle of 8 ns is output from the pattern generator 110, clocks which are delayed by 0 ns at first, delayed by 1 ns at second, delayed by 2 ns at third, and delayed by 3 ns at fourth with respect to the cycle pattern are output from the timing generator. Then, although a clock is delayed by 4 ns at fifth, this is the same as a reference clock cycle, and hence an amount corresponding to this cycle is subtracted, thereby delaying one cycle. That is, since a timing error fluctuates with a cycle of T1≈0.36 ns, spurious noise occurs at a position of 1/T1 with respect to a fundamental frequency.
The fluctuation cycle T2 will now be explained with reference to FIG. 13.
As shown in the drawing, in a case where a reference clock cycle is 4 ns and a RATE frequency set value is 8.0000001192092 ns (=4×2+2−23 ns), if a resolution concerning a setup cycle of the timing generator is 2−7 ns, a cycle pattern having a cycle of 8 ns is output from the pattern generator 110, and a clock whose delay amount is 0 ns from the first to the (216−1) outputs is output from the timing generator 120. Further, the delay becomes 2−7 ns at the next 216 output, a delay path varies in accordance with the cycle T2≈0.524 ms from the first to 216 output, and a phase error also fluctuates. That is, since a timing error fluctuates with the cycle of T2, spurious noise occurs at a position of 1/T2 with respect to a fundamental frequency.
Furthermore, the above-explained spurious noise is removed by the PLL provided in the waveform generation apparatus.
However, the spurious noise removed by the PLL is limited to spurious noise that occurs at a position far from a carrier. That is because a loop filter of the PLL is a low-pass filter, and hence a phase fluctuation of a frequency having a higher rate is apt to be attenuated and an output hardly follows up this attenuation.
Therefore, when a phase of the setup cycle with respect to an integral multiple of a reference clock is large like an example where the setup cycle is 9 ns, since the spurious noise occurs at a position far from the carrier, the PLL can remove the spurious noise. However, when a phase of the setup cycle with respect to an integral multiple of the reference clock is small like an example where the setup cycle is 8.0000001192092 ns, since the spurious noise occurs in the vicinity of the carrier, the PLL can hardly remove the spurious noise.
Such a problem does not occur until a test requiring setting a high-resolution cycle is carried out.
In a conventional test of individually testing respective cores in an electronic device, an operating frequency is generated in accordance with each core. In this case, since a resolution of the cycle setting is low, the spurious noise occurs at a position far from the carrier, e.g., a position of several-ten kHz to several-hundred kHz. Therefore, the PLL can sufficiently remove the spurious noise.
However, in a test requiring setting a high-resolution cycle like a multitime domain, a since a plurality of clocks are synchronized with each core, a resolution of the cycle setting is increased. Then, as shown in FIG. 9, the spurious noise occurs at a position close to the carrier, i.e., a position of several-ten. Hz to several kHz, the PLL cannot remove the spurious noise and outputs it as it is.
Here, as a method of removing (increasing attenuation of) the spurious noise in the vicinity of the carrier, narrowing a loop band of a loop filter 132 can be considered. However, this method has a drawback that frequency switching characteristics are deteriorated when the loop band is narrowed.
Furthermore, since characteristics of a voltage controlled oscillator itself can be more directly reproduced, a caution is required when phase noise of the voltage controlled oscillator is large.
Therefore, the loop band must be subjected to trade-off in accordance with a required specification, e.g., spurious or switching characteristics, and the loop band cannot be reduced limitlessly.